In back-end semiconductor manufacturing—encompassing assembly, advanced packaging, hybrid bonding, panel handling, and final test—ESA (electrostatic attraction) and ESD (electrostatic discharge) increasingly impact yield and long-term reliability. As hybrid bonding pitches shrink below 10 µm and panel-level packaging scales to larger substrates, even minor charge imbalances can drive particle adhesion, bond voids, misalignment, and latent device damage that may not be detected during early testing.
Advanced packaging is now a primary engine of AI-era semiconductor performance, and clean, charge-stable back-end environments are becoming front-end-like in their control requirements—especially for hybrid bonding and PLP workflows.